1. Field of The Invention
This invention relates to a TTL/CMOS compatible input buffer incorporating a Schmitt trigger.
2. Description of The Prior Art
Conventional bipolar integrated circuits operate at low voltage logic levels. Typically, a low or logical "0" for TTL logic circuits ranges from 0.0 to 0.8 volts and a high or logical "1" ranges from 2.0 to 5.0 volts. Thus in order to distinguish between a logical 0 and a logical 1 a CMOS inverter must be capable of switching somewhere between 0.8 and 2.0 volts and preferably at approximately 1.4 volts in order to provide the widest possible noise margin. A CMOS inverter generally operates at voltages of 4.5 to 15 volts with 5 volts being typical. If the source of the P-channel transistor in the CMOS inverter is connected to a voltage of 5 volts, for example, the P-channel transistor will draw a steady state current when a TTL logical "1" as low as 2.0 volts is applied to its gate. Hence it is desirable to establish the switching or trigger point of the CMOS input inverter in a TTL/CMOS buffer at approximately 1.4 volts to maximize noise margins, and to provide a voltage of less than 5 volts on the sources of P-channel transistors in the input buffer in order to reduce steady state power consumption.
To overcome the problem of the differences in operating voltages of the TTL logic circuits and the CMOS circuits, various solutions have been proposed. For example, U.S. Pat. No. 4,471,242 issued Sept. 11, 1984 to Noufer, et al., which is incorporated herein by reference, describes a TTL/CMOS input buffer that accomplished buffering a TTL signal to a CMOS signal with low current flow through a CMOS input inverter in a static (nonswitching) condition. This is achieved by providing a selected reference voltage to the source of the P-channel transistor in the CMOS input inverter. The reference voltage is selected to be less than the lowest voltage level of the TTL logical "1" (2.0 volts) minus the threshold voltage of the P-channel transistor.
Similarly, U.S. Pat. No. 4,475,050 issued to Noufer on Oct. 2, 1984, which is incorporated herein by reference, prevents current flow through the CMOS inverter of the TTL to CMOS input buffer by providing a reference voltage to the source of the P-channel transistor in the input inverter which is responsive to the voltage level of the TTL input signal.
U.S. Pat. No. 4,469,959, issued to Luke et al. on Sept. 4, 1984, which is incorporated herein by reference, describes a bypass means that compensates for the body effect of the load transistor to maintain the switch point of the input inverter stage at a relatively constant value.
When a relatively large number of input buffers are provided in a circuit network, for example as many as 60, if all the inputs are switched simultaneously, the trigger points of the inverters, such as used with the circuit disclosed in the copending patent application, would vary as the reference voltage supplied to the input inverters varies. The greater the number of input buffers that are connected and switched simultaneously, the greater the potential peak-to-peak noise. Simultaneous switching causes a drain on the current source resulting in wiggle of the reference voltage. If the transistion time of an input inverter is slow, such that it intersects with the waveform of the trigger point of the input inverter more than once, the input would be interpreted as having logical level 1010, so that multiple transitions could appear at the output of the input buffer. It would be desirable to reduce the sensitivity to transients and peak-to-peak noise when switching the input stages of the input buffer circuits.